VERIWELL(1)

NAME
Veriwell - manual page for Veriwell 2.8.6,

SYNOPSIS
veriwell [options] <file1> [<file2>...]

DESCRIPTION
'VeriWell' is a Verilog simulator supporting the IEEE 1364-1995 standard.

OPTIONS

-c  Compile only - do not simulate

-s  Enter interactive mode before running

-t  Turn trace on

-f <filename>
    Read options from <filename>

-i <filename>
    Read commands from <filename>

-l <filename>
    Set log file to <filename>

-l nolog
    Disable log file

-k <filename>
    Set key file to <filename>

-k nokey
    Disable key file

-y <directory>
    Search directory for module definitions

-?, -h
    This message

+synopsys
    Enable Synopsys HDL Compiler(tm) 2.x checking

+mindelays
    Use minimum delays

+maxdelays
    Use maximum delays

+typdelays
    Use typical delays

+define+<macro>=<value> Define macros

+libext+<extension>
    Specify library suffix

+incdir+<directory>
    Specify include search path

+<name>+<value>
    Define plusargs

--help
    This message

--version
    Print version

--bindir
    Binary install path

--libdir
    Library install path

--includedir
    Include install path

--cflags
    Compiler flags used

--ldflags
    Linker flags used

--libs
    Libraries used

    All other options are tested for arguments and ignored

EXAMPLES
The following system tasks are supported:

$lxt_recordon
    Enable waveform dump

$lxt_recordoff
    Disable waveform dump

$lxt_recordclose
    End waveform dump

$lxt_recordfile filename options
    Set filename and options

$lxt_recordsetup options
    Set options

$lxt_recordvars options
    Start waveform dump

$lxt2_recordon
    Enable waveform dump

$lxt2_recordoff
    Disable waveform dump

$lxt2_recordclose
    End waveform dump

$lxt2_recordfile filename options
    Set filename and options

$lxt2_recordsetup options
    Set options

$lxt2_recordvars options
    Start waveform dump

  Lxt Options:

incsize=<file_size>
    Specify incremental file size in bytes

space
    optimize for space

speed
    optimize for speed

sequence
    Record 0 time signal changes

nosequence
    Do not record 0 time signal changes

design=<name>
    Specify design name

depth=<depth>
    Specify extraction depth

AUTHOR
Written by Elliot Mednick and Mark Hummel

REPORTING BUGS
Report bugs at <http://sourceforge.net/projects/veriwell>

COPYRIGHT
Copyright © 1993-2008 Elliot Mednick and Mark Hummel

Veriwell comes with ABSOLUTELY NO WARRANTY; This is free software, and you are welcome to redistribute it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.